| Memory Access Test Sequence | |
| uvm_mem_single_access_seq | Verify the accessibility of a memory by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the written value. |
| uvm_mem_access_seq | Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it. |
Verify the accessibility of a memory by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the written value.
If bit-type resource named “NO_REG_TESTS”, “NO_MEM_TESTS”, or “NO_MEM_ACCESS_TEST” in the “REG::” namespace matches the full name of the memory, the memory is not tested.
uvm_resource_db#(bit)::set({"REG::",regmodel.blk.mem0.get_full_name()},
"NO_MEM_TESTS", 1, this);Memories without an available backdoor cannot be tested.
The DUT should be idle and not modify the memory during this test.
| uvm_mem_single_access_seq | |||||||||||
| Verify the accessibility of a memory by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the written value. | |||||||||||
| Class Hierarchy | |||||||||||
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| Class Declaration | |||||||||||
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| Variables | |||||||||||
| mem | The memory to be tested | ||||||||||
Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it.
If bit-type resource named “NO_REG_TESTS”, “NO_MEM_TESTS”, or “NO_MEM_ACCESS_TEST” in the “REG::” namespace matches the full name of the block, the block is not tested.
uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
"NO_MEM_TESTS", 1, this);| uvm_mem_access_seq | |||||||||||
| Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it. | |||||||||||
| Class Hierarchy | |||||||||||
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| Class Declaration | |||||||||||
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| Variables | |||||||||||
| model | The block to be tested. | ||||||||||
| mem_seq | The sequence used to test one memory | ||||||||||
| Methods | |||||||||||
| body | Execute the Memory Access sequence. | ||||||||||
| do_block | Test all of the memories in a given block | ||||||||||
| reset_blk | Reset the DUT that corresponds to the specified block abstraction class. | ||||||||||
The block to be tested. Declared in the base class.
uvm_reg_block model;
virtual task body()
Execute the Memory Access sequence. Do not call directly. Use seq.start() instead.
protected virtual task do_block( uvm_reg_block blk )
Test all of the memories in a given block
virtual task reset_blk( uvm_reg_block blk )
Reset the DUT that corresponds to the specified block abstraction class.
Currently empty. Will rollback the environment’s phase to the reset phase once the new phasing is available.
In the meantime, the DUT should be reset before executing this test sequence or this method should be implemented in an extension to reset the DUT.
Verify the accessibility of a memory by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the written value.
class uvm_mem_single_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it.
class uvm_mem_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
The memory to be tested
uvm_mem mem
The sequence used to test one memory
protected uvm_mem_single_access_seq mem_seq
Execute the Memory Access sequence.
virtual task body()
Test all of the memories in a given block
protected virtual task do_block( uvm_reg_block blk )
Reset the DUT that corresponds to the specified block abstraction class.
virtual task reset_blk( uvm_reg_block blk )