The uvm_root class serves as the implicit top-level and phase controller for all UVM components. Users do not directly instantiate uvm_root. The UVM automatically creates a single instance of uvm_root that users can access via the global (uvm_pkg-scope) variable, uvm_top.
The uvm_top instance of uvm_root plays several key roles in the UVM.
|Implicit top-level||The uvm_top serves as an implicit top-level component. Any component whose parent is specified as NULL becomes a child of uvm_top. Thus, all UVM components in simulation are descendants of uvm_top.|
|Phase control||uvm_top manages the phasing for all components.|
|Search||Use uvm_top to search for components based on their hierarchical name. See find and find_all.|
|Report configuration||Use uvm_top to globally configure report verbosity, log files, and actions. For example, uvm_top.set_report_verbosity_level_hier(UVM_FULL) would set full verbosity for all components in simulation.|
|Global reporter||Because uvm_top is globally accessible (in uvm_pkg scope), UVM’s reporting mechanism is accessible from anywhere outside uvm_component, such as in modules and sequences. See uvm_report_error, uvm_report_warning, and other global methods.|
The uvm_top instance checks during the end_of_elaboration phase if any errors have been generated so far. If errors are found an UVM_FATAL error is being generated as result so that the simulation will not continue to the start_of_simulation_phase.
|The uvm_root class serves as the implicit top-level and phase controller for all UVM components. |
|get()||Get the factory singleton|
|run_test||Phases all components through all registered phases. |
|top_levels||This variable is a list of all of the top level components in UVM. |
|find_all||Returns the component handle (find) or list of components handles (find_all) matching a given string. |
|print_topology||Print the verification environment’s component topology. |
|enable_print_topology||If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase.|
|finish_on_completion||If set, then run_test will call $finish after all phases are executed.|
|set_timeout||Specifies the timeout for the simulation. |
|uvm_top||This is the top-level that governs phase execution and provides component search interface. |
|static function uvm_root get()
Get the factory singleton
|virtual task run_test ( ||string
Phases all components through all registered phases. If the optional test_name argument is provided, or if a command-line plusarg, +UVM_TESTNAME=TEST_NAME, is found, then the specified component is created just prior to phasing. The test may contain new verification components or the entire testbench, in which case the test and testbench can be chosen from the command line without forcing recompilation. If the global (package) variable, finish_on_completion, is set, then $finish is called after phasing completes.
This variable is a list of all of the top level components in UVM. It includes the uvm_test_top component that is created by run_test as well as any other top level components that have been instantiated anywhere in the hierarchy.
|function uvm_component find ( ||string
|function void find_all ( ||
Returns the component handle (find) or list of components handles (find_all) matching a given string. The string may contain the wildcards,
- and ?. Strings beginning with ‘.’ are absolute path names. If optional comp arg is provided, then search begins from that component down (default=all components).
|function void print_topology ( ||uvm_printer
Print the verification environment’s component topology. The printer is a uvm_printer object that controls the format of the topology printout; a null printer prints with the default output.
|bit enable_print_topology = 0
If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase.
|bit finish_on_completion = 1
If set, then run_test will call $finish after all phases are executed.
|function void set_timeout( ||time
Specifies the timeout for the simulation. Default is `UVM_DEFAULT_TIMEOUT
The timeout is simply the maximum absolute simulation time allowed before a FATAL occurs. If the timeout is set to 20ns, then the simulation must end before 20ns, or a FATAL timeout will occur.
This is provided so that the user can prevent the simulation from potentially consuming too many resources (Disk, Memory, CPU, etc) when the testbench is essentially hung.
|const uvm_root uvm_top = uvm_root::get()
This is the top-level that governs phase execution and provides component search interface. See uvm_root for more information.