Phasing

This section describes the set of pre-defined phases provided as a standard part of the UVM library.

Create and configure of testbench structure

uvm_topdown_phase that calls the uvm_component::build_phase method.

Upon entry

• The top-level components have been instantiated under uvm_root.
• Current simulation time is still equal to 0 but some “delta cycles” may have occurred

Typical Uses

• Instantiate sub-components.
• Instantiate register model.
• Get configuration values for the component being built.
• Set configuration values for sub-components.

Exit Criteria

• All uvm_components have been instantiated.

Establish cross-component connections.

uvm_bottomup_phase that calls the uvm_component::connect_phase method.

Upon Entry

• All components have been instantiated.
• Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

• Connect TLM ports and exports.
• Connect TLM initiator sockets and target sockets.
• Connect register model to adapter components.
• Setup explicit phase domains.

Exit Criteria

• All cross-component connections have been established.
• All independent phase domains are set.

Fine-tune the testbench.

uvm_bottomup_phase that calls the uvm_component::end_of_elaboration_phase method.

Upon Entry

• The verification environment has been completely assembled.
• Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

• Display environment topology.
• Open files.
• Define additional configuration settings for components.

Exit Criteria

• None.

Get ready for DUT to be simulated.

uvm_bottomup_phase that calls the uvm_component::start_of_simulation_phase method.

Upon Entry

• Other simulation engines, debuggers, hardware assisted platforms and all other run-time tools have been started and synchronized.
• The verification environment has been completely configured and is ready to start.
• Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

• Display environment topology
• Set debugger breakpoint
• Set initial run-time configuration values.

Exit Criteria

• None.

Stimulate the DUT.

This uvm_task_phase calls the uvm_component::run_phase virtual method.  This phase runs in parallel to the runtime phases, <uvm_pre_reset_ph> through <uvm_post_shutdown_ph>.  All components in the testbench are synchronized with respect to the run phase regardles of the phase domain they belong to.

Upon Entry

• Indicates that power has been applied.
• There should not have been any active clock edges before entry into this phase (e.g. x->1 transitions via initial blocks).
• Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

• Components implement behavior that is exhibited for the entire run-time, across the various run-time phases.
• Backward compatibility with OVM.

Exit Criteria

• The DUT no longer needs to be simulated, and
• The <uvm_post_shutdown_ph> is ready to end

The run phase terminates in one of four ways.

1.  Explicit call to <global_stop_request>

When <global_stop_request> is called, an ordered shut-down for the run phase begins.  First, all enabled components’ <uvm_component::stop> tasks are called bottom-up, i.e., childrens’ <uvm_component::stop> tasks are called before the parent’s.

Stopping a component is enabled by its uvm_component::enable_stop_interrupt bit.  Each component can implement <uvm_component::stop> to allow completion of in-progress transactions, flush queues, and other shut-down activities.  Upon return from <uvm_component::stop> by all enabled components, the run phase becomes ready to end pending completion of the runtime phases (i.e. the <uvm_post_shutdown_ph> being ready to end.

If any component raised a phase objection in uvm_component::run_phase(), this stopping procedure is deferred until all outstanding objections have been dropped.

2.  All run phase objections have been dropped after having been raised

When all objections on the run phase objection have been dropped by the uvm_component::run_phase() methods, <global_stop_request> is called automatically, thus kicking off the stopping procedure described above.

If no component ever raises a phase objection, this termination mechanism never happens.

3.  Explicit call to uvm_component::kill or uvm_component::do_kill_all

When uvm_component::kill is called, that component’s uvm_component::run_phase processes are killed immediately.  The uvm_component::do_kill_all methods applies to the component and all its descendants.

Use of this method is not recommended.  It is better to use the stopping mechanism, which affords a more ordered, safer shut-down.  If an immediate termination is desired, a <uvm_component::jump> to the <uvm_extract_ph> phase is recommended as this will cause both the run phase and the parallel runtime phases to immediately end and go to extract.

4.  Timeout

The phase ends if the timeout expires before an explicit call to <global_stop_request> or uvm_component::kill.  By default, the timeout is set to 0, which is no timeout.  You may override this via <set_global_timeout>.

If a timeout occurs in your simulation, or if simulation never ends despite completion of your test stimulus, then it usually indicates a missing call to <global_stop_request>.

Extract data from different points of the verficiation environment.

uvm_bottomup_phase that calls the uvm_component::extract_phase method.

Upon Entry

• The DUT no longer needs to be simulated.
• Simulation time will no longer advance.

Typical Uses

• Extract any remaining data and final state information from scoreboard and testbench components
• Probe the DUT (via zero-time hierarchical references and/or backdoor accesses) for final state information.
• Compute statistics and summaries.
• Display final state information
• Close files.

Exit Criteria

• All data has been collected and summarized.

Check for any unexpected conditions in the verification environment.

uvm_bottomup_phase that calls the uvm_component::check_phase method.

Upon Entry

• All data has been collected.

Typical Uses

• Check that no unaccounted-for data remain.

Exit Criteria

• Test is known to have passed or failed.

Report results of the test.

uvm_bottomup_phase that calls the uvm_component::report_phase method.

Upon Entry

• Test is known to have passed or failed.

Typical Uses

• Report test results.
• Write results to file.

Exit Criteria

• End of test.

Tie up loose ends.

uvm_topdown_phase that calls the uvm_component::final_phase method.

Upon Entry

• All test-related activity has completed.

Typical Uses

• Close files.
• Terminate co-simulation engines.

Exit Criteria

• Ready to exit simulator.

Before reset is asserted.

uvm_task_phase that calls the uvm_component::pre_reset_phase method.  This phase starts at the same time as the <uvm_run_ph> unless a user defined phase is inserted in front of this phase.

Upon Entry

• Indicates that power has been applied but not necessarily valid or stable.
• There should not have been any active clock edges before entry into this phase.

Typical Uses

• Wait for power good.
• Components connected to virtual interfaces should initialize their output to X’s or Z’s.
• Initialize the clock signals to a valid value
• Assign reset signals to X (power-on reset).
• Wait for reset signal to be asserted if not driven by the verification environment.

Exit Criteria

• Reset signal, if driven by the verification environment, is ready to be asserted.
• Reset signal, if not driven by the verification environment, is asserted.

Reset is asserted.

uvm_task_phase that calls the uvm_component::reset_phase method.

Upon Entry

• Indicates that the hardware reset signal is ready to be asserted.

Typical Uses

• Assert reset signals.
• Components connected to virtual interfaces should drive their output to their specified reset or idle value.
• Components and environments should initialize their state variables.
• Clock generators start generating active edges.
• De-assert the reset signal(s) just before exit.
• Wait for the reset signal(s) to be de-asserted.

Exit Criteria

• Reset signal has just been de-asserted.
• Main or base clock is working and stable.
• At least one active clock edge has occurred.
• Output signals and state variables have been initialized.

After reset is de-asserted.

uvm_task_phase that calls the uvm_component::post_reset_phase method.

Upon Entry

• Indicates that the DUT reset signal has been de-asserted.

Typical Uses

• Components should start behavior appropriate for reset being inactive.  For example, components may start to transmit idle transactions or interface training and rate negotiation.  This behavior typically continues beyond the end of this phase.

Exit Criteria

• The testbench and the DUT are in a known, active state.

Before the DUT is configured by the SW.

uvm_task_phase that calls the uvm_component::pre_configure_phase method.

Upon Entry

• Indicates that the DUT has been completed reset and is ready to be configured.

Typical Uses

• Procedurally modify the DUT configuration information as described in the environment (and that will be eventually uploaded into the DUT).
• Wait for components required for DUT configuration to complete training and rate negotiation.

Exit Criteria

• DUT configuration information is defined.

The SW configures the DUT.

uvm_task_phase that calls the uvm_component::configure_phase method.

Upon Entry

• Indicates that the DUT is ready to be configured.

Typical Uses

• Components required for DUT configuration execute transactions normally.
• Set signals and program the DUT and memories (e.g. read/write operations and sequences) to match the desired configuration for the test and environment.

Exit Criteria

• The DUT has been configured and is ready to operate normally.

After the SW has configured the DUT.

uvm_task_phase that calls the uvm_component::post_configure_phase method.

Upon Entry

• Indicates that the configuration information has been fully uploaded.

Typical Uses

• Wait for configuration information to fully propagate and take effect.
• Wait for components to complete training and rate negotiation.
• Enable the DUT.
• Sample DUT configuration coverage.

Exit Criteria

• The DUT has been fully configured and enabled and is ready to start operating normally.

Before the primary test stimulus starts.

uvm_task_phase that calls the uvm_component::pre_main_phase method.

Upon Entry

• Indicates that the DUT has been fully configured.

Typical Uses

• Wait for components to complete training and rate negotiation.

Exit Criteria

• All components have completed training and rate negotiation.
• All components are ready to generate and/or observe normal stimulus.

Primary test stimulus.

uvm_task_phase that calls the uvm_component::main_phase method.

Upon Entry

• The stimulus associated with the test objectives is ready to be applied.

Typical Uses

• Components execute transactions normally.
• Data stimulus sequences are started.
• Wait for a time-out or certain amount of time, or completion of stimulus sequences.

Exit Criteria

• Enough stimulus has been applied to meet the primary stimulus objective of the test.

After enough of the primary test stimulus.

uvm_task_phase that calls the uvm_component::post_main_phase method.

Upon Entry

• The primary stimulus objective of the test has been met.

Typical Uses

• Included for symmetry.

Exit Criteria

• None.

Before things settle down.

uvm_task_phase that calls the uvm_component::pre_shutdown_phase method.

Upon Entry

• None.

Typical Uses

• Included for symmetry.

Exit Criteria

• None.

Letting things settle down.

uvm_task_phase that calls the uvm_component::shutdown_phase method.

Upon Entry

• None.

Typical Uses

• Wait for all data to be drained out of the DUT.
• Extract data still buffered in the DUT, usually through read/write operations or sequences.

Exit Criteria

• All data has been drained or extracted from the DUT.
• All interfaces are idle.

After things have settled down.

uvm_task_phase that calls the uvm_component::post_shutdown_phase method.  The end of this phase is synchronized to the end of the <uvm_run_ph> phase unless a user defined phase is added after this phase.

Upon Entry

• No more “data” stimulus is applied to the DUT.

Typical Uses

• Perform final checks that require run-time access to the DUT (e.g. read accounting registers or dump the content of memories).

Exit Criteria

• All run-time checks have been satisfied.
• The <uvm_run_ph> phase is ready to end.

To defined your own custom phase, use the following pattern

1. extend the appropriate base class for your phase type

class my_PHASE_phase extends uvm_task_phase("PHASE");
class my_PHASE_phase extends uvm_topdown_phase("PHASE");
class my_PHASE_phase extends uvm_bottomup_phase("PHASE");

2. implement your exec_task or exec_func method

task exec_task(uvm_component comp, uvm_phase schedule);
function void exec_func(uvm_component comp, uvm_phase schedule);

3. the implementation usually calls the related method on the component

comp.PHASE_phase(uvm_phase phase);

4. after declaring your phase singleton class, instantiate one for global use

static my_``PHASE``_phase my_``PHASE``_ph = new();

5. insert the phase in a phase schedule or domain using the uvm_phase::add method inside your VIP base class’s definition of the <uvm_phase::define_domain> method.

The API described here provides a general purpose testbench phasing solution, consisting of a phaser machine, traversing a master schedule graph, which is built by the integrator from one or more instances of template schedules provided by UVM or by 3rd-party VIP, and which supports implicit or explicit synchronization, runtime control of threads and jumps.

Each schedule leaf node refers to a single phase that is compatible with that VIP’s components and which executes the required behavior via a functor or delegate extending the phase into component context as required.  Execution threads are tracked on a per-component basis and various thread semantics available to allow defined phase control and responsibility.

Class hierarchy

A single class represents both the definition, the state, and the context of a phase.  It is instantiated once as a singleton IMP and one or more times as nodes in a graph which represents serial and parallel phase relationships and stores current state as the phaser progresses, and the phase implementation which specifies required component behavior (by extension into component context if non-default behavior required.)

The following classes related to phasing are defined herein

uvm_phase : The base class for defining a phase’s behavior, state, context

uvm_bottomup_phase : A phase implemenation for bottom up function phases.

uvm_topdown_phase : A phase implemenation for topdown function phases.

uvm_task_phase : A phase implemenation for task phases.

This base class defines everything about a phase: behavior, state, and context

To define behavior, it is extended by UVM or the user to create singleton objects which capture the definition of what the phase does and how it does it.  These are then cloned to produce multiple nodes which are hooked up in a graph structure to provide context: which phases follow which, and to hold the state of the phase throughout its lifetime.  UVM provides default extensions of this class for the standard runtime phases.  VIP Providers can likewise extend this class to define the phase functor for a particular component context as required.

Phase Definition

Singleton instances of those extensions are provided as package variables.  These instances define the attributes of the phase (not what state it is in) They are then cloned into schedule nodes which point back to one of these implementations, and calls it’s virtual task or function methods on each participating component.  It is the base class for phase functors, for both predefined and user-defined phases.  Per-component overrides can use a customized imp.

To create custom phases, do not extend uvm_phase directly: see the three predefined extended classes below which encapsulate behavior for different phase types: task, bottom-up function and top-down function.

Extend the appropriate one of these to create a uvm_YOURNAME_phase class (or YOURPREFIX_NAME_phase class) for each phase, containing the default implementation of the new phase, which must be a uvm_component-compatible delegate, and which may be a null implementation.  Instantiate a singleton instance of that class for your code to use when a phase handle is required.  If your custom phase depends on methods that are not in uvm_component, but are within an extended class, then extend the base YOURPREFIX_NAME_phase class with parameterized component class context as required, to create a specialized functor which calls your extended component class methods.  This scheme ensures compile-safety for your extended component classes while providing homogeneous base types for APIs and underlying data structures.

Phase Context

A schedule is a coherent group of one or mode phase/state nodes linked together by a graph structure, allowing arbitrary linear/parallel relationships to be specified, and executed by stepping through them in the graph order.  Each schedule node points to a phase and holds the execution state of that phase, and has optional links to other nodes for synchronization.

The main build operations are: construct, add phases, and instantiate hierarchically within another schedule.

Structure is a DAG (Directed Acyclic Graph).  Each instance is a node connected to others to form the graph.  Hierarchy is overlaid with m_parent.  Each node in the graph has zero or more successors, and zero or more predecessors.  No nodes are completely isolated from others.  Exactly one node has zero predecessors.  This is the root node.  Also the graph is acyclic, meaning for all nodes in the graph, by following the forward arrows you will never end up back where you started but you will eventually reach a node that has no successors.

Phase State

A given phase may appear multiple times in the complete phase graph, due to the multiple independent domain feature, and the ability for different VIP to customize their own phase schedules perhaps reusing existing phases.  Each node instance in the graph maintains its own state of execution.

Phase Handle

Handles of this type uvm_phase are used frequently in the API, both by the user, to access phasing-specific API, and also as a parameter to some APIs.  In many cases, the singleton package-global phase handles can be used (eg. connect_ph, run_ph) in APIs.  For those APIs that need to look up that phase in the graph, this is done automatically.

Phasing schedule node representing an independent branch of the schedule.  Handle used to assign domains to components or hierarchies in the testbench

Virtual base class for function phases that operate bottom-up.  The pure virtual function execute() is called for each component.  This is the default traversal so is included only for naming.

A bottom-up function phase completes when the execute() method has been called and returned on all applicable components in the hierarchy.

Virtual base class for function phases that operate top-down.  The pure virtual function execute() is called for each component.

A top-down function phase completes when the execute() method has been called and returned on all applicable components in the hierarchy.

Base class for all task phases.  It forks a call to uvm_phase::exec_task() for each component in the hierarchy.

A task phase completes when there are no raised objections to the end of phase.  The completion of the task does not imply, nor is it required for, the end of phase.  Once the phase completes, any remaining forked uvm_phase::exec_task() threads are forcibly and immediately killed.

The only way for a task phase to extend over time is if there is at least one component that raises an objection.

class my_comp extends uvm_component;
   task main_phase(uvm_phase phase);
      phase.raise_objection(this, "Applying stimulus")
      ...
      phase.drop_objection(this, "Applied enough stimulus")
   endtask
endclass