The uvm_root class serves as the implicit top-level and phase controller for all UVM components. Users do not directly instantiate uvm_root. The UVM automatically creates a single instance of uvm_root that users can access via the global (uvm_pkg-scope) variable, uvm_top.
The uvm_top instance of uvm_root plays several key roles in the UVM.
Implicit top-level | The uvm_top serves as an implicit top-level component. Any component whose parent is specified as NULL becomes a child of uvm_top. Thus, all UVM components in simulation are descendants of uvm_top. |
Phase control | uvm_top manages the phasing for all components. TBD |
Search | Use uvm_top to search for components based on their hierarchical name. See find and find_all. |
Report configuration | Use uvm_top to globally configure report verbosity, log files, and actions. For example, uvm_top.set_report_verbosity_level_hier(UVM_FULL) would set full verbosity for all components in simulation. |
Global reporter | Because uvm_top is globally accessible (in uvm_pkg scope), UVM’s reporting mechanism is accessible from anywhere outside uvm_component, such as in modules and sequences. See uvm_report_error, uvm_report_warning, and other global methods. |
uvm_root | |
The uvm_root class serves as the implicit top-level and phase controller for all UVM components. | |
Methods | |
run_test | Phases all components through all registered phases. |
Variables | |
top_levels | This variable is a list of all of the top level components in UVM. |
Methods | |
find | |
find_all | Returns the component handle (find) or list of components handles (find_all) matching a given string. |
print_topology | Print the verification environment’s component topology. |
Variables | |
enable_print_topology | If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase. |
finish_on_completion | If set, then run_test will call $finish after all phases are executed. |
Methods | |
set_timeout | Specifies the timeout for task-based phases. |
Variables | |
uvm_top | This is the top-level that governs phase execution and provides component search interface. |
virtual task run_test ( string test_name = "" )
Phases all components through all registered phases. If the optional test_name argument is provided, or if a command-line plusarg, +UVM_TESTNAME=TEST_NAME, is found, then the specified component is created just prior to phasing. The test may contain new verification components or the entire testbench, in which case the test and testbench can be chosen from the command line without forcing recompilation. If the global (package) variable, finish_on_completion, is set, then $finish is called after phasing completes.
uvm_component top_levels[$]
This variable is a list of all of the top level components in UVM. It includes the uvm_test_top component that is created by run_test as well as any other top level components that have been instantiated anywhere in the hierarchy.
function uvm_component find ( string comp_match )
function void find_all ( string comp_match, ref uvm_component comps[$], input uvm_component comp = null )
Returns the component handle (find) or list of components handles (find_all) matching a given string. The string may contain the wildcards,
function void print_topology ( uvm_printer printer = null )
Print the verification environment’s component topology. The printer is a uvm_printer object that controls the format of the topology printout; a null printer prints with the default output.
bit enable_print_topology = 0
If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase.
bit finish_on_completion = 1
If set, then run_test will call $finish after all phases are executed.
function void set_timeout( time timeout, bit overridable = 1 )
Specifies the timeout for task-based phases. Default is 0, i.e. no timeout.
Phases all components through all registered phases.
virtual task run_test ( string test_name = "" )
This variable is a list of all of the top level components in UVM.
uvm_component top_levels[$]
function uvm_component find ( string comp_match )
Returns the component handle (find) or list of components handles (find_all) matching a given string.
function void find_all ( string comp_match, ref uvm_component comps[$], input uvm_component comp = null )
Print the verification environment’s component topology.
function void print_topology ( uvm_printer printer = null )
If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase.
bit enable_print_topology = 0
If set, then run_test will call $finish after all phases are executed.
bit finish_on_completion = 1
Specifies the timeout for task-based phases.
function void set_timeout( time timeout, bit overridable = 1 )
This is the top-level that governs phase execution and provides component search interface.
const uvm_root uvm_top = uvm_root::get()
function void uvm_report_error( string id, string message, int verbosity = UVM_LOW, string filename = "", int line = 0 )
function void uvm_report_warning( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0 )
The uvm_printer class provides an interface for printing uvm_objects in various formats.
virtual class uvm_printer