This section defines the base classes used for register stimulus generation. It also defines a predictor component, which is used to update the register model’s mirror values based on transactions observed on a physical bus.
| Register Sequence and Predictor Classes | This section defines the base classes used for register stimulus generation. |
| uvm_reg_sequence | This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”. |
| uvm_reg_frontdoor | Facade class for register and memory frontdoor access. |
| uvm_reg_predictor | Updates the register model mirror based on observed bus transactions |
This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
Register operations do not require extending this class if none of the above services are needed. Register test sequences can be extend from the base uvm_sequence #(REQ,RSP) base class or even from outside a sequence.
Note- The convenience API not yet implemented.
| uvm_reg_sequence | |||||||||||||||||
| This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”. | |||||||||||||||||
| Class Hierarchy | |||||||||||||||||
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| Class Declaration | |||||||||||||||||
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| BASE | Specifies the sequence type to extend from. | ||||||||||||||||
| model | Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. | ||||||||||||||||
| adapter | Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. | ||||||||||||||||
| reg_seqr | Layered upstream “register” sequencer. | ||||||||||||||||
| new | Create a new instance, giving it the optional name. | ||||||||||||||||
| body | Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via <do_rw_access>. | ||||||||||||||||
| do_reg_item | Executes the given register transaction, rw, via the sequencer on which this sequence was started (i.e. | ||||||||||||||||
| Convenience Write/ Read API | The following methods delegate to the corresponding method in the register or memory element. | ||||||||||||||||
| write_reg | Writes the given register rg using uvm_reg::write, supplying ‘this’ as the parent argument. | ||||||||||||||||
| read_reg | Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument. | ||||||||||||||||
| poke_reg | Pokes the given register rg using uvm_reg::poke, supplying ‘this’ as the parent argument. | ||||||||||||||||
| peek_reg | Peeks the given register rg using uvm_reg::peek, supplying ‘this’ as the parent argument. | ||||||||||||||||
| update_reg | Updates the given register rg using uvm_reg::update, supplying ‘this’ as the parent argument. | ||||||||||||||||
| mirror_reg | Mirrors the given register rg using uvm_reg::mirror, supplying ‘this’ as the parent argument. | ||||||||||||||||
| write_mem | Writes the given memory mem using uvm_mem::write, supplying ‘this’ as the parent argument. | ||||||||||||||||
| read_mem | Reads the given memory mem using uvm_mem::read, supplying ‘this’ as the parent argument. | ||||||||||||||||
| poke_mem | Pokes the given memory mem using uvm_mem::poke, supplying ‘this’ as the parent argument. | ||||||||||||||||
| peek_mem | Peeks the given memory mem using uvm_mem::peek, supplying ‘this’ as the parent argument. | ||||||||||||||||
Specifies the sequence type to extend from.
When used as a translation sequence running on a bus sequencer, BASE must be compatible with the sequence type expected by the bus sequencer.
When used as a test sequence running on a particular sequencer, BASE must be compatible with the sequence type expected by that sequencer.
When used as a virtual test sequence without a sequencer, BASE does not need to be specified, i.e. the default specialization is adequate.
To maximize opportunities for reuse, user-defined RegModel sequences should “promote” the BASE parameter.
class my_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item))
extends uvm_reg_sequence #(BASE);This way, the RegModel sequence can be extended from user-defined base sequences.
uvm_reg_block model
Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.
uvm_reg_adapter adapter
Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.
uvm_sequencer #( uvm_reg_item ) reg_seqr
Layered upstream “register” sequencer.
Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to “pull” from an upstream sequencer.
function new ( string name = "uvm_reg_sequence_inst" )
Create a new instance, giving it the optional name.
virtual task body()
Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via <do_rw_access>.
User-defined RegModel test sequences must override body() and not call super.body(), else a warning will be issued and the calling process not return.
virtual task do_reg_item( uvm_reg_item rw )
Executes the given register transaction, rw, via the sequencer on which this sequence was started (i.e. m_sequencer). Uses the configured adapter to convert the register transaction into the type expected by this sequencer.
The following methods delegate to the corresponding method in the register or memory element. They allow a sequence body() to do reads and writes without having to explicitly supply itself to parent sequence argument. Thus, a register write
model.regA.write(status, value, .parent(this));
can be written instead as
write_reg(model.regA, status, value);
virtual task write_reg( input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Writes the given register rg using uvm_reg::write, supplying ‘this’ as the parent argument. Thus,
write_reg(model.regA, status, value);
is equivalent to
model.regA.write(status, value, .parent(this));
virtual task read_reg( input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument. Thus,
read_reg(model.regA, status, value);
is equivalent to
model.regA.read(status, value, .parent(this));
virtual task poke_reg( input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Pokes the given register rg using uvm_reg::poke, supplying ‘this’ as the parent argument. Thus,
poke_reg(model.regA, status, value);
is equivalent to
model.regA.poke(status, value, .parent(this));
virtual task peek_reg( input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Peeks the given register rg using uvm_reg::peek, supplying ‘this’ as the parent argument. Thus,
peek_reg(model.regA, status, value);
is equivalent to
model.regA.peek(status, value, .parent(this));
virtual task update_reg( input uvm_reg rg, output uvm_status_e status, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Updates the given register rg using uvm_reg::update, supplying ‘this’ as the parent argument. Thus,
update_reg(model.regA, status, value);
is equivalent to
model.regA.update(status, value, .parent(this));
virtual task mirror_reg( input uvm_reg rg, output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Mirrors the given register rg using uvm_reg::mirror, supplying ‘this’ as the parent argument. Thus,
mirror_reg(model.regA, status, UVM_CHECK);
is equivalent to
model.regA.mirror(status, UVM_CHECK, .parent(this));
virtual task write_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Writes the given memory mem using uvm_mem::write, supplying ‘this’ as the parent argument. Thus,
write_mem(model.regA, status, offset, value);
is equivalent to
model.regA.write(status, offset, value, .parent(this));
virtual task read_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Reads the given memory mem using uvm_mem::read, supplying ‘this’ as the parent argument. Thus,
read_mem(model.regA, status, offset, value);
is equivalent to
model.regA.read(status, offset, value, .parent(this));
virtual task poke_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Pokes the given memory mem using uvm_mem::poke, supplying ‘this’ as the parent argument. Thus,
poke_mem(model.regA, status, offset, value);
is equivalent to
model.regA.poke(status, offset, value, .parent(this));
virtual task peek_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Peeks the given memory mem using uvm_mem::peek, supplying ‘this’ as the parent argument. Thus,
peek_mem(model.regA, status, offset, value);
is equivalent to
model.regA.peek(status, offset, value, .parent(this));
Facade class for register and memory frontdoor access.
User-defined frontdoor access sequence
Base class for user-defined access to register and memory reads and writes through a physical interface.
By default, different registers and memories are mapped to different addresses in the address space and are accessed via those exclusively through physical addresses.
The frontdoor allows access using a non-linear and/or non-mapped mechanism. Users can extend this class to provide the physical access to these registers.
| uvm_reg_frontdoor | |||||||||||
| Facade class for register and memory frontdoor access. | |||||||||||
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| rw_info | Holds information about the register being read or written | ||||||||||
| sequencer | Sequencer executing the operation | ||||||||||
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| new | Constructor, new object givne optional name. | ||||||||||
Updates the register model mirror based on observed bus transactions
This class converts observed bus transactions of type BUSTYPE to generic registers transactions, determines the register being accessed based on the bus address, then updates the register’s mirror value with the observed bus data, subject to the register’s access mode. See uvm_reg::predict for details.
Memories can be large, so their accesses are not predicted. Users can periodically use backdoor peek/poke to update the memory mirror.
| uvm_reg_predictor | |||||||||||||||||
| Updates the register model mirror based on observed bus transactions | |||||||||||||||||
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| Class Declaration | |||||||||||||||||
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| bus_in | Observed bus transactions of type BUSTYPE are received from this port and processed. | ||||||||||||||||
| reg_ap | Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in. | ||||||||||||||||
| map | The map used to convert a bus address to the corresponding register or memory handle. | ||||||||||||||||
| adapter | The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum. | ||||||||||||||||
| Methods | |||||||||||||||||
| new | Create a new instance of this type, giving it the optional name and parent. | ||||||||||||||||
| pre_predict | Override this method to change the value or re-direct the target register | ||||||||||||||||
| check_phase | Checks that no pending register transactions are still enqueued. | ||||||||||||||||
uvm_analysis_imp #( BUSTYPE, uvm_reg_predictor #(BUSTYPE) ) bus_in
Observed bus transactions of type BUSTYPE are received from this port and processed.
For each incoming transaction, the predictor will attempt to get the register or memory handle corresponding to the observed bus address.
If there is a match, the predictor calls the register or memory’s predict method, passing in the observed bus data. The register or memory mirror will be updated with this data, subject to its configured access behavior--RW, RO, WO, etc. The predictor will also convert the bus transaction to a generic uvm_reg_item and send it out the reg_ap analysis port.
If the register is wider than the bus, the predictor will collect the multiple bus transactions needed to determine the value being read or written.
uvm_analysis_port #( uvm_reg_item ) reg_ap
Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in.
uvm_reg_map map
The map used to convert a bus address to the corresponding register or memory handle. Must be configured before the run phase.
uvm_reg_adapter adapter
The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum. The adapter must be configured before the run phase.
function new ( string name, uvm_component parent )
Create a new instance of this type, giving it the optional name and parent.
virtual function void pre_predict( uvm_reg_item rw )
Override this method to change the value or re-direct the target register
virtual function void check_phase( uvm_phase phase )
Checks that no pending register transactions are still enqueued.
This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
class uvm_reg_sequence #( type BASE = uvm_sequence #(uvm_reg_item) ) extends BASE
Facade class for register and memory frontdoor access.
virtual class uvm_reg_frontdoor extends uvm_reg_sequence #( uvm_sequence #(uvm_sequence_item) )
Updates the register model mirror based on observed bus transactions
class uvm_reg_predictor #( type BUSTYPE = int ) extends uvm_component
Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.
uvm_reg_block model
Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.
uvm_reg_adapter adapter
Layered upstream “register” sequencer.
uvm_sequencer #( uvm_reg_item ) reg_seqr
Create a new instance, giving it the optional name.
function new ( string name = "uvm_reg_sequence_inst" )
Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_rw_access.
virtual task body()
Executes the given register transaction, rw, via the sequencer on which this sequence was started (i.e.
virtual task do_reg_item( uvm_reg_item rw )
Writes the given register rg using uvm_reg::write, supplying ‘this’ as the parent argument.
virtual task write_reg( input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Write the specified value in this register
virtual task write( output uvm_status_e status, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument.
virtual task read_reg( input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Read the current value from this register
virtual task read( output uvm_status_e status, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Pokes the given register rg using uvm_reg::poke, supplying ‘this’ as the parent argument.
virtual task poke_reg( input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Deposit the specified value in this register
virtual task poke( output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Peeks the given register rg using uvm_reg::peek, supplying ‘this’ as the parent argument.
virtual task peek_reg( input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Read the current value from this register
virtual task peek( output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Updates the given register rg using uvm_reg::update, supplying ‘this’ as the parent argument.
virtual task update_reg( input uvm_reg rg, output uvm_status_e status, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Updates the content of the register in the design to match the desired value
virtual task update( output uvm_status_e status, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Mirrors the given register rg using uvm_reg::mirror, supplying ‘this’ as the parent argument.
virtual task mirror_reg( input uvm_reg rg, output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Read the register and update/check its mirror value
virtual task mirror( output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Writes the given memory mem using uvm_mem::write, supplying ‘this’ as the parent argument.
virtual task write_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Write the specified value in a memory location
virtual task write( output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Reads the given memory mem using uvm_mem::read, supplying ‘this’ as the parent argument.
virtual task read_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Read the current value from a memory location
virtual task read( output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Pokes the given memory mem using uvm_mem::poke, supplying ‘this’ as the parent argument.
virtual task poke_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Deposit the specified value in a memory location
virtual task poke( output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Peeks the given memory mem using uvm_mem::peek, supplying ‘this’ as the parent argument.
virtual task peek_mem( input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0 )
Read the current value from a memory location
virtual task peek( output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0 )
The uvm_sequence class provides the interfaces necessary in order to create streams of sequence items and/or other sequences.
virtual class uvm_sequence #( type REQ = uvm_sequence_item, type RSP = REQ ) extends uvm_sequence_base
Holds information about the register being read or written
uvm_reg_item rw_info
Sequencer executing the operation
uvm_sequencer_base sequencer
Constructor, new object givne optional name.
function new( string name = "" )
The uvm_object class is the base class for all UVM data and hierarchical classes.
virtual class uvm_object extends uvm_void
The uvm_report_object provides an interface to the UVM reporting facility.
class uvm_report_object extends uvm_object
The uvm_component class is the root base class for UVM components.
virtual class uvm_component extends uvm_report_object
Observed bus transactions of type BUSTYPE are received from this port and processed.
uvm_analysis_imp #( BUSTYPE, uvm_reg_predictor #(BUSTYPE) ) bus_in
Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in.
uvm_analysis_port #( uvm_reg_item ) reg_ap
Defines an abstract register transaction item.
class uvm_reg_item extends uvm_sequence_item
The map used to convert a bus address to the corresponding register or memory handle.
uvm_reg_map map
The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum.
uvm_reg_adapter adapter
Create a new instance of this type, giving it the optional name and parent.
function new ( string name, uvm_component parent )
Override this method to change the value or re-direct the target register
virtual function void pre_predict( uvm_reg_item rw )
Checks that no pending register transactions are still enqueued.
virtual function void check_phase( uvm_phase phase )
Update the mirrored value for this register.
virtual function bit predict ( uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_path_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0 )