uvm_reg_mem_built_in_seq

Sequence that executes a user-defined selection of pre-defined register and memory test sequences.

Summary
uvm_reg_mem_built_in_seq
Sequence that executes a user-defined selection of pre-defined register and memory test sequences.
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_reg_mem_built_in_seq
Class Declaration
class uvm_reg_mem_built_in_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Variables
modelThe block to be tested.
testsThe pre-defined test sequences to be executed.
Methods
bodyExecutes any or all the built-in register and memory sequences.

model

The block to be tested.  Declared in the base class.

uvm_reg_block model;

tests

bit [63:0] tests = UVM_DO_ALL_REG_MEM_TESTS

The pre-defined test sequences to be executed.

body

virtual task body()

Executes any or all the built-in register and memory sequences.  Do not call directly.  Use seq.start() instead.

class uvm_reg_mem_built_in_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Sequence that executes a user-defined selection of pre-defined register and memory test sequences.
bit [63:0] tests = UVM_DO_ALL_REG_MEM_TESTS
The pre-defined test sequences to be executed.
virtual task body()
Executes any or all the built-in register and memory sequences.