The sequence is started and the uvm_sequence_base::body() task is being executed.
The sequence has been allocated.
End of request phase
End of response phase
The sequence has completed the execution of the uvm_sequence_base::body() task.
The sequence is completely finished executing.
The sequence is started and the uvm_sequence_base::post_body() task is being executed.
The sequence is started and the uvm_sequence_base::post_start() task is being executed.
The sequence is started and the uvm_sequence_base::pre_body() task is being executed.
The sequence is started and the uvm_sequence_base::pre_start() task is being executed.
Requests are granted in FIFO order (default)
Requests are granted randomly
Requests at highest priority granted in fifo order
Requests at highest priority granted in randomly
Arbitration is delegated to the user-defined function, user_priority_arbitration.
Requests are granted randomly by weight
The sequence has been forcibly ended by issuing a uvm_sequence_base::kill() on the sequence.
Defaults for constructor
all objections have been dropped
Use the back door
Most-significant bytes first in consecutive addresses
Most-significant bytes first at the same address
Selects binary (%b) format
Callback the report hook methods
Read and check
the phase completed normally
Counts the number of reports with the COUNT attribute.
Individual register and memory addresses
All coverage models
Field values
Individual register bits
Selects decimal (%d) format
Objects are deep copied (object must implement copy method)
Operation specified by the context
Sends the report to the standard output
Run all of the above
Run uvm_mem_access_seq
Run uvm_mem_walk_seq
Run uvm_reg_access_seq
Run uvm_reg_bit_bash_seq
Run uvm_reg_hw_reset_seq
Run uvm_reg_mem_shared_access_seq
an objection was raised
Selects enumeration value (name) format
equal
Indicates a real problem.
Terminates the simulation immediately.
The port provides the interface that is its type parameter via a connection to some other export or implementation.
Indicates a problem from which simulation can not recover.
Field
the phase was forced to terminate prematurely
Use the front door
Report is issued if configured verbosity is set to UVM_FULL or above.
greater than
greater than or equal to
Operation completed successfully bit had unknown bits.
Selects hexidecimal (%h) format
Provide info based on the hierarchical context
Report is issued if configured verbosity is set to UVM_HIGH or above.
The port provides the interface that is its type parameter, and it is bound to the component that implements the interface.
Informative messsage.
Operation completed successfully
Least-significant bytes first in consecutive addresses
Least-significant bytes first at the same address
Sends the report to the file(s) for this (severity,id) pair
Report is issued if configured verbosity is set to UVM_LOW or above.
less than
less than or equal to
Report is issued if configured verbosity is set to UVM_MEDIUM or above.
Memory location
not equal
No action is taken
Read only
None
Byte ordering not applicable
Provide info from the local context
Report is always printed.
Operation completed with error
Selects octal (%o) format
all processes related to phase are being killed
This object represents an entire graph segment that executes in parallel with the ‘run’ phase.
A phase is done after it terminated execution.
Nothing has happened with the phase in this domain.
phase completed execution, now running phase_ended() callback
An executing phase is one where the phase callbacks are being executed.
The phase object is used to traverse the component hierarchy and call the component phase method as well as the phase_started and phase_ended callbacks.
The object represents a simple node instance in the graph.
no objections remain, awaiting completion of predecessors of its successors.
The object represents a portion of the phasing graph, typically consisting of several NODE types, in series, parallel, or both.
At least one immediate predecessor has completed.
phase ready to execute, running phase_started() callback
All predecessors complete, checking that all synced phases (e.g.
This internal object serves as the termination NODE for a SCHEDULE phase object.
The port requires the interface that is its type parameter.
Operation derived from observations by a bus monitor via the uvm_reg_predictor class.
Predicted value is as-is
Predict based on the specified value having been read
Predict based on the specified value having been written
an objection was raised
Read operation
Only object handles are copied.
Register
the phase was in the path of a backwards jump
Emit only items, no sequence execution
Random sequence selection
Random cyclic sequence selection
Apply a user-defined random-selection algorithm
Objects are shallow copied using default SV copy.
the phase was in the path of a forward jump
Causes $stop to be executed, putting the simulation into interactive mode.