Verify the correctness of HDL paths specified for registers and memories.
This sequence is be used to check that the specified backdoor paths are indeed accessible by the simulator. By default, the check is performed for the default design abstraction. If the simulation contains multiple models of the DUT, HDL paths for multiple design abstractions can be checked.
If a path is not accessible by the simulator, it cannot be used for read/write backdoor accesses. In that case a warning is produced. A simulator may have finer-grained access permissions such as separate read or write permissions. These extra access permissions are NOT checked.
The test is performed in zero time and does not require any reads/writes to/from the DUT.
|Verify the correctness of HDL paths specified for registers and memories.|
|class uvm_reg_mem_hdl_paths_seq extends uvm_reg_sequence #( |
|abstractions||If set, check the HDL paths for the specified design abstractions. |