The uvm_agent virtual class should be used as the base class for the user- defined agents.
virtual class uvm_agent extends uvm_component
Compares two streams of data objects of different types, BEFORE and AFTER.
class uvm_algorithmic_comparator #( type BEFORE = int, type AFTER = int, type TRANSFORMER = int ) extends uvm_component
Exports a lower-level uvm_analysis_imp to its parent.
class uvm_analysis_export #( type T = int ) extends uvm_port_base #(uvm_tlm_if_base #(T,T))
Receives all transactions broadcasted by a uvm_analysis_port.
class uvm_analysis_imp #( type T = int, type IMP = int ) extends uvm_port_base #(uvm_tlm_if_base #(T,T))
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.
class uvm_analysis_port # ( type T = int ) extends uvm_port_base # (uvm_tlm_if_base #(T,T))
The uvm_barrier class provides a multiprocess synchronization mechanism.
class uvm_barrier extends uvm_object
Virtual base class for function phases that operate bottom-up.
virtual class uvm_bottomup_phase extends uvm_phase
Create and configure of testbench structure
class uvm_build_phase extends uvm_topdown_phase
This policy class is used to clone built-in types via the = operator.
class uvm_built_in_clone #( type T = int )
This policy class is used to compare built-in types.
class uvm_built_in_comp #( type T = int )
This policy class is used to convert built-in types to strings.
class uvm_built_in_converter #( type T = int )
Container holding two variables of built-in types (int, string, etc.)
class uvm_built_in_pair #( type T1 = int, T2 = T1 ) extends uvm_object
The uvm_callback class is the base class for user-defined callback classes.
class uvm_callback extends uvm_object
The uvm_callback_iter class is an iterator class for iterating over callback queues of a specific callback type.
class uvm_callback_iter#( type T = uvm_object, type CB = uvm_callback )
The uvm_callbacks class provides a base class for implementing callbacks, which are typically used to modify or augment component behavior without changing the component class.
class uvm_callbacks #( type T = uvm_object, type CB = uvm_callback ) extends uvm_typed_callbacks#(T)
The uvm_callbacks_objection is a specialized uvm_objection which contains callbacks for the raised and dropped events.
class uvm_callbacks_objection extends uvm_objection
Check for any unexpected conditions in the verification environment.
class uvm_check_phase extends uvm_bottomup_phase
This policy class is used to clone class objects.
class uvm_class_clone #( type T = int )
This policy class is used to compare two objects of the same type.
class uvm_class_comp #( type T = int )
This policy class is used to convert a class object to a string.
class uvm_class_converter #( type T = int )
Container holding handles to two objects whose types are specified by the type parameters, T1 and T2.
class uvm_class_pair #( type T1 = int, T2 = T1 ) extends uvm_object
This class provides an interface to the command line arguments that were provided for the given simulation.
class uvm_cmdline_processor extends uvm_report_object
The uvm_comparer class provides a policy object for doing comparisons.
class uvm_comparer
The uvm_component class is the root base class for UVM components.
virtual class uvm_component extends uvm_report_object
The uvm_component_registry serves as a lightweight proxy for a component of type T and type name Tname, a string.
class uvm_component_registry #( type T = uvm_component, string Tname = "<unknown>" ) extends uvm_object_wrapper
All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator.
class uvm_config_db#( type T = int ) extends uvm_resource_db#(T)
The SW configures the DUT.
class uvm_configure_phase extends uvm_task_phase
Establish cross-component connections.
class uvm_connect_phase extends uvm_bottomup_phase
Phasing schedule node representing an independent branch of the schedule.
class uvm_domain extends uvm_phase
The base class for drivers that initiate requests for new transactions via a uvm_seq_item_pull_port.
class uvm_driver #( type REQ = uvm_sequence_item, type RSP = REQ ) extends uvm_component
Fine-tune the testbench.
class uvm_end_of_elaboration_phase extends uvm_bottomup_phase
The base class for hierarchical containers of other components that together comprise a complete environment.
virtual class uvm_env extends uvm_component
The uvm_event class is a wrapper class around the SystemVerilog event construct.
class uvm_event extends uvm_object
The uvm_event_callback class is an abstract class that is used to create callback objects which may be attached to uvm_events.
virtual class uvm_event_callback extends uvm_object
Extract data from different points of the verficiation environment.
class uvm_extract_phase extends uvm_bottomup_phase
As the name implies, uvm_factory is used to manufacture (create) UVM objects and components.
class uvm_factory
Tie up loose ends.
class uvm_final_phase extends uvm_topdown_phase
Concatenation of HDL variables
class uvm_hdl_path_concat
This class uses the uvm_built_in_* comparison, converter, and pair classes.
class uvm_in_order_built_in_comparator #( type T = int ) extends uvm_in_order_comparator #(T)
This class uses the uvm_class_* comparison, converter, and pair classes.
class uvm_in_order_class_comparator #( type T = int ) extends uvm_in_order_comparator #( T , uvm_class_comp #( T ) , uvm_class_converter #( T ) , uvm_class_pair #( T, T ) )
The line printer prints output in a line format.
class uvm_line_printer extends uvm_tree_printer
Primary test stimulus.
class uvm_main_phase extends uvm_task_phase
Memory abstraction base class
class uvm_mem extends uvm_object
Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it.
class uvm_mem_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Memory allocation manager
class uvm_mem_mam
Specifies the memory managed by an instance of a uvm_mem_mam memory allocation manager class.
class uvm_mem_mam_cfg
An instance of this class is randomized to determine the starting offset of a randomly allocated memory region.
class uvm_mem_mam_policy
Allocated memory region descriptor
class uvm_mem_region
Verify the accessibility of a shared memory by writing through each address map then reading it via every other address maps in which the memory is readable and the backdoor, making sure that the resulting value matches the written value.
class uvm_mem_shared_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Verify the accessibility of a memory by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the written value.
class uvm_mem_single_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Runs the walking-ones algorithm on the memory given by the mem property, which must be assigned prior to starting this sequence.
class uvm_mem_single_walk_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Verifies the all memories in a block by executing the uvm_mem_single_walk_seq sequence on every memory within it.
class uvm_mem_walk_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
This class should be used as the base class for user-defined monitors.
virtual class uvm_monitor extends uvm_component
The uvm_object class is the base class for all UVM data and hierarchical classes.
virtual class uvm_object extends uvm_void
The uvm_object_registry serves as a lightweight proxy for an uvm_object of type T and type name Tname, a string.
class uvm_object_registry #( type T = uvm_object, string Tname = "<unknown>" ) extends uvm_object_wrapper
This provides a specialization of the generic uvm_pool #(KEY,T) class for an associative array of uvm_object-based objects indexed by string.
class uvm_object_string_pool #( type T = uvm_object ) extends uvm_pool #(string,T)
The uvm_object_wrapper provides an abstract interface for creating object and component proxies.
virtual class uvm_object_wrapper
Objections provide a facility for coordinating status information between two or more participating components, objects, and even module-based IP.
class uvm_objection extends uvm_report_object
The uvm_objection is the callback type that defines the callback implementations for an objection callback.
class uvm_objection_callback extends uvm_callback
This base class defines everything about a phase: behavior, state, and context.
class uvm_phase extends uvm_object
Implements a class-based dynamic associative array.
class uvm_pool #( type KEY = int, T = uvm_void ) extends uvm_object
Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.
virtual class uvm_port_base #( type IF = uvm_void ) extends IF
See description of uvm_port_component_base for information about this class
class uvm_port_component #( type PORT = uvm_object ) extends uvm_port_component_base
This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase.
virtual class uvm_port_component_base extends uvm_component
After the SW has configured the DUT.
class uvm_post_configure_phase extends uvm_task_phase
After enough of the primary test stimulus.
class uvm_post_main_phase extends uvm_task_phase
After reset is de-asserted.
class uvm_post_reset_phase extends uvm_task_phase
After things have settled down.
class uvm_post_shutdown_phase extends uvm_task_phase
Before the DUT is configured by the SW.
class uvm_pre_configure_phase extends uvm_task_phase
Before the primary test stimulus starts.
class uvm_pre_main_phase extends uvm_task_phase
Before reset is asserted.
class uvm_pre_reset_phase extends uvm_task_phase
Before things settle down.
class uvm_pre_shutdown_phase extends uvm_task_phase
The uvm_printer class provides an interface for printing uvm_objects in various formats.
virtual class uvm_printer
The uvm_printer_knobs class defines the printer settings available to all printer subtypes.
class uvm_printer_knobs
Base class for a driver that passively receives transactions, i.e.
class uvm_push_driver #( type REQ = uvm_sequence_item, type RSP = REQ ) extends uvm_component
class uvm_push_sequencer #( type REQ = uvm_sequence_item, RSP = REQ ) extends uvm_sequencer_param_base #(REQ, RSP)
Implements a class-based dynamic queue.
class uvm_queue #( type T = int ) extends uvm_object
A general purpose unidirectional random stimulus class.
class uvm_random_stimulus #( type T = uvm_transaction ) extends uvm_component
The uvm_recorder class provides a policy object for recording uvm_objects.
class uvm_recorder extends uvm_object
Register abstraction base class
virtual class uvm_reg extends uvm_object
Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.
class uvm_reg_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
This class defines an interface for converting between uvm_reg_bus_op and a specific bus transaction.
virtual class uvm_reg_adapter extends uvm_object
Base class for user-defined back-door register and memory access.
class uvm_reg_backdoor extends uvm_object
Verify the implementation of all registers in a block by executing the uvm_reg_single_bit_bash_seq sequence on it.
class uvm_reg_bit_bash_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Block abstraction base class
virtual class uvm_reg_block extends uvm_object
Facade class for field, register, memory and backdoor access callback methods.
virtual class uvm_reg_cbs extends uvm_callback
Field abstraction class
class uvm_reg_field extends uvm_object
This special register models a DUT FIFO accessed via write/read, where writes push to the FIFO and reads pop from it.
class uvm_reg_fifo extends uvm_reg
Register file abstraction base class
virtual class uvm_reg_file extends uvm_object
Facade class for register and memory frontdoor access.
virtual class uvm_reg_frontdoor extends uvm_reg_sequence #( uvm_sequence #(uvm_sequence_item) )
Test the hard reset values of registers
class uvm_reg_hw_reset_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Indirect data access abstraction class
class uvm_reg_indirect_data extends uvm_reg
Defines an abstract register transaction item.
class uvm_reg_item extends uvm_sequence_item
class uvm_reg_map extends uvm_object
Verify the accessibility of all registers and memories in a block by executing the uvm_reg_access_seq and uvm_mem_access_seq sequence respectively on every register and memory within it.
class uvm_reg_mem_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Sequence that executes a user-defined selection of pre-defined register and memory test sequences.
class uvm_reg_mem_built_in_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Verify the correctness of HDL paths specified for registers and memories.
class uvm_reg_mem_hdl_paths_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.
class uvm_reg_mem_shared_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Updates the register model mirror based on observed bus transactions
class uvm_reg_predictor #( type BUSTYPE = int ) extends uvm_component
Pre-defined register callback method for read-only registers that will issue an error if a write() operation is attempted.
class uvm_reg_read_only_cbs extends uvm_reg_cbs
This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
class uvm_reg_sequence #( type BASE = uvm_sequence #(uvm_reg_item) ) extends BASE
Verify the accessibility of a shared register by writing through each address map then reading it via every other address maps in which the register is readable and the backdoor, making sure that the resulting value matches the mirrored value.
class uvm_reg_shared_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Verify the accessibility of a register by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the mirrored value.
class uvm_reg_single_access_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
Verify the implementation of a single register by attempting to write 1’s and 0’s to every bit in it, via every address map in which the register is mapped, making sure that the resulting value matches the mirrored value.
class uvm_reg_single_bit_bash_seq extends uvm_reg_sequence #( uvm_sequence #(uvm_reg_item) )
For converting between uvm_reg_bus_op and uvm_tlm_gp items.
class uvm_reg_tlm_adapter extends uvm_reg_adapter
Pre-defined register callback method for write-only registers that will issue an error if a read() operation is attempted.
class uvm_reg_write_only_cbs extends uvm_reg_cbs
The uvm_report_catcher is used to catch messages issued by the uvm report server.
virtual class uvm_report_catcher extends uvm_callback
The uvm_report_object provides an interface to the UVM reporting facility.
class uvm_report_object extends uvm_object
Report results of the test.
class uvm_report_phase extends uvm_bottomup_phase
Reset is asserted.
class uvm_reset_phase extends uvm_task_phase
Parameterized resource.
class uvm_resource #( type T = int ) extends uvm_resource_base
Non-parameterized base class for resources.
virtual class uvm_resource_base extends uvm_object
All of the functions in uvm_resource_db#(T) are static, so they must be called using the :: operator.
class uvm_resource_db #( type T = uvm_object )
The global (singleton) resource database.
class uvm_resource_pool
Provides typedefs and enums used throughout the resources facility.
class uvm_resource_types
Stimulate the DUT.
class uvm_run_phase extends uvm_task_phase
The uvm_scoreboard virtual class should be used as the base class for user-defined scoreboards.
virtual class uvm_scoreboard extends uvm_component
This export type is used in sequencer-driver communication.
class uvm_seq_item_pull_export #( type REQ = int, type RSP = REQ ) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP))
This imp type is used in sequencer-driver communication.
class uvm_seq_item_pull_imp #( type REQ = int, type RSP = REQ, type IMP = int ) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP))
UVM provides a port, export, and imp connector for use in sequencer-driver communication.
class uvm_seq_item_pull_port #( type REQ = int, type RSP = REQ ) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP))
The uvm_sequence class provides the interfaces necessary in order to create streams of sequence items and/or other sequences.
virtual class uvm_sequence #( type REQ = uvm_sequence_item, type RSP = REQ ) extends uvm_sequence_base
The uvm_sequence_base class provides the interfaces needed to create streams of sequence items and/or other sequences.
class uvm_sequence_base extends uvm_sequence_item
The base class for user-defined sequence items and also the base class for the uvm_sequence class.
class uvm_sequence_item extends uvm_transaction
class uvm_sequencer #( type REQ = uvm_sequence_item, RSP = REQ ) extends uvm_sequencer_param_base #(REQ, RSP)
Controls the flow of sequences, which generate the stimulus (sequence item transactions) that is passed on to drivers for execution.
class uvm_sequencer_base extends uvm_component
Extends uvm_sequencer_base with an API depending on specific request (REQ) and response (RSP) types.
class uvm_sequencer_param_base #( type REQ = uvm_sequence_item, type RSP = REQ ) extends uvm_sequencer_base
Letting things settle down.
class uvm_shutdown_phase extends uvm_task_phase
This class defines an interface for sequence drivers to communicate with sequencers.
virtual class uvm_sqr_if_base #( type T1 = uvm_object, T2 = T1 )
Get ready for DUT to be simulated.
class uvm_start_of_simulation_phase extends uvm_bottomup_phase
This class provides an analysis export for receiving transactions from a connected analysis export.
virtual class uvm_subscriber #( type T = int ) extends uvm_component
The table printer prints output in a tabular format.
class uvm_table_printer extends uvm_printer
Base class for all task phases.
virtual class uvm_task_phase extends uvm_phase
This class is the virtual base class for the user-defined tests.
virtual class uvm_test extends uvm_component
An analysis_fifo is a uvm_tlm_fifo with an unbounded size and a write interface.
class uvm_tlm_analysis_fifo #( type T = int ) extends uvm_tlm_fifo #(T)
IS-A forward port; has no backward path except via the payload contents
class uvm_tlm_b_initiator_socket #( type T = uvm_tlm_generic_payload ) extends uvm_tlm_b_initiator_socket_base #(T)
IS-A forward port; has no backward path except via the payload contents
class uvm_tlm_b_initiator_socket_base #( type T = uvm_tlm_generic_payload ) extends uvm_port_base #(uvm_tlm_if #(T))
IS-A forward port;
class uvm_tlm_b_passthrough_initiator_socket #( type T = uvm_tlm_generic_payload ) extends uvm_tlm_b_passthrough_initiator_socket_base #(T)
IS-A forward port
class uvm_tlm_b_passthrough_initiator_socket_base #( type T = uvm_tlm_generic_payload ) extends uvm_port_base #(uvm_tlm_if #(T))
IS-A forward export;
class uvm_tlm_b_passthrough_target_socket #( type T = uvm_tlm_generic_payload ) extends uvm_tlm_b_passthrough_target_socket_base #(T)
IS-A forward export
class uvm_tlm_b_passthrough_target_socket_base #( type T = uvm_tlm_generic_payload ) extends uvm_port_base #(uvm_tlm_if #(T))
IS-A forward imp; has no backward path except via the payload contents.
class uvm_tlm_b_target_socket #( type IMP = int, type T = uvm_tlm_generic_payload ) extends uvm_tlm_b_target_socket_base #(T)
IS-A forward imp; has no backward path except via the payload contents.
class uvm_tlm_b_target_socket_base #( type T = uvm_tlm_generic_payload ) extends uvm_port_base #(uvm_tlm_if #(T))
Blocking transport export class.
class uvm_tlm_b_transport_export #( type T = uvm_tlm_generic_payload ) extends uvm_port_base #(uvm_tlm_if #(T))
Used like exports, except an addtional class parameter specifices the type of the implementation object.
class uvm_tlm_b_transport_imp #( type T = uvm_tlm_generic_payload, type IMP = int ) extends uvm_port_base #(uvm_tlm_if #(T))
Class providing the blocking transport port, The port can be bound to one export.
class uvm_tlm_b_transport_port #( type T = uvm_tlm_generic_payload ) extends uvm_port_base #(uvm_tlm_if #(T))
TLM extension class.
class uvm_tlm_extension #( type T = int ) extends uvm_tlm_extension_base
The class uvm_tlm_extension_base is the non-parameterized base class for all generic payload extensions.
virtual class uvm_tlm_extension_base extends uvm_object
This class provides storage of transactions between two independently running processes.
class uvm_tlm_fifo #( type T = int ) extends uvm_tlm_fifo_base #(T)
This class is the base for uvm_tlm_fifo #(T).
virtual class uvm_tlm_fifo_base #( type T = int ) extends uvm_component
This class provides a transaction definition commonly used in memory-mapped bus-based systems.
class uvm_tlm_generic_payload extends uvm_sequence_item
This typedef provides a short, more convenient name for the uvm_tlm_generic_payload type.
typedef uvm_tlm_generic_payload uvm_tlm_gp
Base class type to define the transport functions.
class uvm_tlm_if #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e )
This class declares all of the methods of the TLM API.
virtual class uvm_tlm_if_base #( type T1 = int, type T2 = int )
IS-A forward port; HAS-A backward imp
class uvm_tlm_nb_initiator_socket #( type IMP = int, type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_tlm_nb_initiator_socket_base #(T,P)
IS-A forward port; HAS-A backward imp
class uvm_tlm_nb_initiator_socket_base #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
IS-A forward port; HAS-A backward export
class uvm_tlm_nb_passthrough_initiator_socket #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_tlm_nb_passthrough_initiator_socket_base #(T,P)
IS-A forward port; HAS-A backward export
class uvm_tlm_nb_passthrough_initiator_socket_base #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
IS-A forward export; HAS-A backward port
class uvm_tlm_nb_passthrough_target_socket #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_tlm_nb_passthrough_target_socket_base #(T,P)
IS-A forward export; HAS-A backward port
class uvm_tlm_nb_passthrough_target_socket_base #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
IS-A forward imp; HAS-A backward port
class uvm_tlm_nb_target_socket #( type IMP = int, type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_tlm_nb_target_socket_base #(T,P)
IS-A forward imp; HAS-A backward port
class uvm_tlm_nb_target_socket_base #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
Non-blocking backward transport export class
class uvm_tlm_nb_transport_bw_export #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
Used like exports, except an addtional class parameter specifices the type of the implementation object.
class uvm_tlm_nb_transport_bw_imp #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e, type IMP = int ) extends uvm_port_base #(uvm_tlm_if #(T,P))
Class providing the non-blocking backward transport port.
class uvm_tlm_nb_transport_bw_port #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
Non-blocking forward transport export class
class uvm_tlm_nb_transport_fw_export #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
Used like exports, except an addtional class parameter specifices the type of the implementation object.
class uvm_tlm_nb_transport_fw_imp #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e, type IMP = int ) extends uvm_port_base #(uvm_tlm_if #(T,P))
Class providing the non-blocking backward transport port.
class uvm_tlm_nb_transport_fw_port #( type T = uvm_tlm_generic_payload, type P = uvm_tlm_phase_e ) extends uvm_port_base #(uvm_tlm_if #(T,P))
The uvm_tlm_req_rsp_channel contains a request FIFO of type REQ and a response FIFO of type RSP.
class uvm_tlm_req_rsp_channel #( type REQ = int, type RSP = REQ ) extends uvm_component
Canonical time type that can be used in different timescales
class uvm_tlm_time
A uvm_tlm_transport_channel is a uvm_tlm_req_rsp_channel #(REQ,RSP) that implements the transport interface.
class uvm_tlm_transport_channel #( type REQ = int, type RSP = REQ ) extends uvm_tlm_req_rsp_channel #(REQ, RSP)
Virtual base class for function phases that operate top-down.
virtual class uvm_topdown_phase extends uvm_phase
The uvm_transaction class is the root base class for UVM transactions.
virtual class uvm_transaction extends uvm_object
By overriding various methods of the uvm_printer super class, the tree printer prints output in a tree format.
class uvm_tree_printer extends uvm_printer
Virtual register abstraction base class
class uvm_vreg extends uvm_object
Pre/post read/write callback facade class
class uvm_vreg_cbs extends uvm_callback
Virtual field abstraction class
class uvm_vreg_field extends uvm_object
Pre/post read/write callback facade class
class uvm_vreg_field_cbs extends uvm_callback